1. Technical Field
The present invention relates generally to an improved data processing system, and in particular to a method and apparatus for transferring data. Still more particularly, the present invention provides a method and apparatus for multi-context direct memory access.
2. Description of the Related Art
Transmission of packets between data processing systems involves a number of steps. Data within a data processing system is collected through a feature, such as direct memory access (DMA). The data is assembled into a single packet and sent across a communications link to a target data processing system. The packet includes a header and a payload. The header includes information identifying the target, payload type, source, and various control data as specified by the protocol while the payload holds the data that is transmitted. When a packet is received at a data processing system, the packet is parsed to see if the packet is intended for the data processing system.
IEEE 1394 is an international serial bus standard. This standard provides a low cost digital interface that can be used for multimedia applications. Data may be transported at 100, 200, or 400 megabits per second as per the IEEE 1394-1995 Annex J Phys-Link Interface Specification. A 1394 serial bus supports two types of data transfer: asynchronous and isochronous. Asynchronous data transfer emphasizes delivery of data at the expense of no guaranteed bandwidth to deliver the data. Data packets are sent and an acknowledgment is returned. If a data defect is present, the packet can be resent. In contrast, iscochronous data transfer guarantees the data transmission bandwidth through channel allocation, but cannot resend defective data packets. This type of transfer is especially useful with multimedia data.
Currently, on a data processing system using the 1394 standard, a link, providing the interface to the 1394 serial bus, must parse a received packet to determine whether to accept the packet and whether to acknowledge acceptance of a packet. If the packet is accepted, the link places the packet into a buffer configured as a first-in-first-out (FIFO) buffer. On the other side of the FIFO buffer in the data processing system is a DMA engine that removes the packet and parses the packet in a manner similar to the link.
In currently available adapters used to move data between a host bus and a 1394 serial bus, DMA engines are phase dependent. When a device is in an isochronous phase, only isochronous DMA processes will function. In an asynchronous phase, only asynchronous DMA functions will process. As a result, presently available devices will not prepare an isochronous transmission during an asynchronous time or prepare an asynchronous transmission during an isochronous time period. This situation is not a major problem for an asynchronous period because an asynchronous transmission may occur during any idle time in the bus. Isochronous periods however terminate when the bus goes idle for a period called a subtraction gap. As a result, possible difficulties for isochronous transmissions may occur when the host bus is too busy to supply data to the isochronous transmit FIFO during an available window of an isochronous period. This is especially true if the only isochronous transmitter is the host device itself. In such a situation, the only time that the FIFO would be filled for the next isochronous cycle would be during the duration of a previous loaded packet plus the subtraction gap time. As a result, these bus phase dependencies reduce the efficiency and speed of data transfer.
Therefore, it would be advantageous to have an improved method and apparatus for transferring data in a data processing system in which multiple contexts are employed.
The present invention provides a method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.